The present disclosure relates generally to microelectronic devices and, more specifically, to a microelectronic device having a multi-sided source/drain silicide or other contact, a method of manufacture therefor, and an integrated circuit incorporating the same.
Transistors and other semiconductor devices typically include source and drain regions on opposing sides of a gate stack. Vias or other interconnects extend through one or more dielectric layers over the transistors, thereby contacting the source and drain regions to interconnect the transistors. Conventionally, the areas of the source and drain regions contacted by the vias include a silicide layer to decrease resistance between the vias and the source and drain regions.
However, as device scaling continues, the source and drain regions and the silicide contacts become progressively thinner. Consequently, the contact resistance at the junction between the vias and the source and drain regions becomes increasingly difficult to maintain within desired quantitative ranges.
Device scaling is also limited by the diameter of the vias and other interconnects extending through the interlevel dielectric layers of the interconnect structure. That is, while the feature size of active devices may be further decreased, a minimum contact area must be maintained for each source and drain region contacted by a via in order to decrease the contact resistance at the junction thereof and provide sufficient ohmic contact.
Accordingly, what is needed in the art is a device and method of manufacture thereof that addresses the above-discussed issues.